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CS485xx
CS485xx Family Data Sheet
Features
? Cost-effective, High-performance 32-bit DSP
Differentiating from the legacy Cirrus multi-standard, multi-channel
decoders, this new CS485xx family is still based on the same
high-performance 32-bit fixed point Digital Signal Processor core
?
?
300,000,000 MAC/S (multiply accumulates per second)
Dual MAC cycles per clock
but instead is equipped with much less memory, tailoring it for more
cost-effective applications associated with multi-channel and
virtual-channel sound enhancements. Target applications are:
? 72-bit accumulators are the most accurate in the industry
? 24k x 32 SRAM, 2k blocks - assignable to data or program
? Internal ROM contains a variety of configurable sound
enhancement feature sets
? 8-channel internal DMA
? Internal watch-dog DSP lock-up prevention
? DSP Tool Set w/ Private Keys for Protecting Customer IP
? Configurable Serial Audio Inputs/Outputs
? Digital Televisions
? Multimedia Peripherals
? iPod ? Docking Stations
? Automotive Head Units
? Automotive Outboard Amplifiers
? HD-DVD ? and Blu-ray Disc ? DVD Receivers
? PC Speakers
There are also a wide variety of licensable DSP codes available
?
?
?
?
?
?
Configurable for all input/output types
Maximum 32-bit @ 192 kHz
Supports 32-bit audio sample I/O between DSP chips
TDM input modes (multiple channels on same line)
192 kHz SPDIF transmitter
Multi-channel DSD direct stream digital SACD input
today as seen by the following examples:
? Supports Two Different Input Fs Sample Rates
?
?
?
?
Output can be master or slave
Dual processing path capability
Input supports dual domain slave clocking
Hardware assist time sampling for sample rate conversion
Cirrus also has developed, or is developing their own royalty-free
versions of popular features sets like Cirrus Bass Manager, Cirrus
Dynamic Volume Leveler, Cirrus Original Multichannel Surround,
Cirrus Virtual Speaker & Cirrus 3D-Audio.
? Integrated Clock Manager/PLL
? Can operate from external crystal, external oscillator
? Input Fs Auto Detection
? Host & Boot via Serial Interface
? Configurable GPIOs and External Interrupt Input
? 1.8V Core and a 3.3V I/O that is tolerant to 5V input
? Low-power Mode
? “Energy Star ? Ready” in low-power mode, 268 μW in standby
The CS485xx family is programmed using the Cirrus proprietary
DSP Composer ? GUI development tool. Processing chains may be
designed using a drag-and-drop interface to place/utilize functional
macro audio DSP primitives. The end result is a software image that
is down-loaded to the DSP via serial host or serial boot modes.
See Section 6 for ordering information.
12 Ch. Audio In /
6 Ch. SACD In
Serial
Control 1
GPIO
Debug
Watchdog
S/PDIF
P
32-bit
DSP
X
Y
D
M
A
TMR1
TMR2
12 Ch PCM
Audio Out
PLL
CS485xx Block Diagram
http://www.cirrus.com
Copyright ? Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS734F5
OCT '11
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